2. News

2.1 Version v1.5
2.2 Version v1.4
2.3 Version v1.3
2.4 Version v1.2
2.5 Version v1.1
2.6 Version v1.0

2.1 Version v1.5

Date: 05Jan28

VTracer is a family of subprojects which can be used as tools for solving various problems, arising during Verilog Testbench development.

The last tool in the sequence is called Vcosim, Verilog-Perl co-simulation platform. This platform enables interoperability between Verilog and Perl processes, and on-the-fly transferring of information between the 2 domains.

The current demo demonstrates Verilog interoperability with Perl, while the user may use the same platform with any other language along with Verilog (TCL, Python, C/C++ etc.).

The current release includes:

• Website re-designed (http://VTracer.sf.net).

• Vcosim (Verilog-Perl co-simulation platform) modifications:
  • A new family of VPI (PLI 2.0) routines defined.
  • The platform is ported to Synopsys VCS simulator (previously, only Icarus simulator was supported)

2.2 Version v1.4

Date: 04Oct31

This release includes Verilog co-simulation environment (Vcosim).
The co-simulation environment uses TCP sockets protocol.
The demo consists of a simple Verilog Testbench (client side) and a Perl memory model (server side).

The server side may be implemented in another language (Perl, TCL, Python, C/C++ etc.).

2.3 Version v1.3

Date: 04Aug25

This release includes Structural Verilog parser.
The parser analyzes Verilog netlist and returns information on design structure,
logic cones, self-contained logic clouds, etc.

2.4 Version v1.2

Date: 04Jul26

VTracer is a ASIC developer assistance tool.
It analyzes VCD dump file created on a simulation, and performs many helpful tasks, including:

• Comparing 2 different VCD files, each one produced by another simulation.
  Helpful for automatization of signals comparison;
• Creating stimuli file for a Testbench, based on a VCD produced by another Testbench.
  Helpful during Testbench development, integration of design cores into a complex SOC, etc.
• Automatic creation of signal pointers module. This new module can be easily integrated
  into a Testbench, and it proves to be very helpful for finding/analyzing all important
  signals without need for browsing the design hierarchy.

• Client-server configuration model. The server (TCL script) communicates
  with the client (Perl script) via TCP socket (inter-process communication).
• User-interace is done through the server only, via shell-like interface;
  there is a set of user commands which enable the user to control the flow on-the-fly.

2.5 Version v1.1

Date: 04Jun24

New features in this release:

1. The whole VTracer verification loop is demonstrated:
   • Native Testbench generates the reference VCD dump file;
   • Verilog stimuli is generated from this VCD file;
   • The stimuli file feeds the device into the new Testbench; another VCD file is generated;
   • The 2 VCD's are compared - verification loop is closed.
2. Website updated (http://VTracer.sf.net)

3. Documentation updated.

Enjoy!

2.6 Version v1.0

Daet: 04Jun20

Verilog designers spend hours comparing VCD traces of different simulations. For example, when integrating an ASIC core into a SoC, the 1st trace is produced by the core verification environment. The 2nd trace is produced by applying the same stimuli to the inputs of the core after integration. Verifying that the outputs produced by the 2 Testbenches may be a tedious process.

VTracer is the solution. Version 1.0 was currently released.

The current release performs traces comparison. In the future releases, automated stimuli generation from the VCD trace will be implemented.

The release includes a sample Testbench demonstrating the tool integration with risc8 RISC core.