4. Vcosim (Verilog-Perl co-simulation platform)

4.1 Vcosim introduction
4.2 Vcosim system requirements
4.3 Vcosim running flow
4.4 Vcosim Perl library
4.5 Vcosim Testbench
4.6 Vcosim VPI routines
4.7 Vcosim data formats

4.1 Vcosim introduction

Vcosim is a Verilog-Perl co-simulation environment.
The co-simulation environment enables developing of simulation models outside the Verilog domain. The environment is based on the TCP socket client-slave communication protocol, where the Verilog simulation serves as client, and the server can be developed in any other language (Perl, TCL, C/C++ etc.).

The current release demonstrates the Vcosim consisting of the following elements:

• Verilog Testbench (client side).
• Server side, written in Perl. The current demo server application contains a simplified memory model.
• Client-server communication layer, written is VPI (PLI 2.0) and C. This layer is built upon TCP sockets communication protocol.

Advantages of the socket-based co-simulation model:

• Client and server side are 2 different applications, completely separated from each other.
• Server side can be implemented in any language (Perl, TCL, Python, C/C++ etc.).

4.2 Vcosim system requirements

• The Vcosim co-simulation environment was tested on the following platforms:
  • RedHat 7.2
  • SuSE 9.1

• The environment was ported to the following Verilog simulators:
  • Icarus Verilog simulator (v8.0) (default).
  • Synopsys VCS simulator

• Optionally, if you need to analyze dump (VCD) files, one of the following viewers should be available:
  • GTKWave dump (VCD) viewer (default).
  • Synopsys Virsim dump viewer

4.3 Vcosim running flow

Go to the simulation start point:

cd vtracer/vcosim/sim

The flow is managed by the main script (../bin/run_vcosim.pl). Read the script options:

../bin/run_vcosim.pl -help

Launch the server:

../bin/run_vcosim.pl -server

Run the demo simulation:

../bin/run_vcosim.pl -run

Each time when the server is launched, an old server process is killed.
If you need to kill the server process implicitly:

../bin/run_vcosim.pl -kill

You can choose the Verilog simulator to work with (Icarus is selected by default):

../bin/run_vcosim.pl -sim <icarus|vcs> -run

There is a dump (VCD) file generated by the demo simulation.
You can open it with GTKWave viewer:

../bin/run_vcosim.pl -gtkwave

Or with Synopsys Virsim viewer:

../bin/run_vcosim.pl -virsim

In addition to the ../bin/run_vcosim.pl script, you can use the local Makefile, which enables more flexibility than the ../bin/run_vcosim.pl script, but requires a certain level of experience with `Makefile's.

4.4 Vcosim Perl library

Vcosim environment's server side can be implemented in many forms. The current implementation demonstrates the server written in Perl. The Vcosim Perl library, located under `vtracer/vcosim/lib_perl/Vcosim' directory, performs all the needed tasks:

• TCP socket server-side communication control.

• Foreign model imlpementation. The "foreign model" can be any user-defined application. The current demo demonstrates a simple memory model. This model exists as a separate process running simultaneously with the Verilog simulation. The Testbench (client) initializes the interactions with the model via one of the pre-defined VPI routines, and the model responds to these requests.

  Notice that the foreign model can serve a sequence of separate Verilog simulations, which can be useful for regression tests developing.

• General purpose Perl routines. Using the co-simulation environment, it is possible to build various functions in Perl, instead Verilog, and the result value of such functions is passed to a Verilog signal or bus.
  The current delivery implements 2 such functions:
  • "square" (result = x^2)
  • "multiply" (result = x*y)

4.5 Vcosim Testbench

The Verilog Testbench files reside under vtracer/vcosim/simenv/tb directory.
The Testbench top module of Vcosim instanciates a Verilog module (in the current demo this module's name is mem_wrapper). The purpose of this module is to "hide" (wrap) the interface to the foreign model (Perl). The "wrapper" module sends/receives data to/from the foreign model through a set of Vcosim VPI tasks (in the current demo, memory read, write and init are implemented).

In order to simulate the real world situation, where the data from the foreign model may be undefined, the "wrapper", between the transactions, masks the data received from the foreign model with X's.

4.6 Vcosim VPI routines

Any user-defined Perl subroutine can be called from the Verilog domain (Testbench) using one of the pre-defined Vcosim VPI routines. The VPI code resides under vtracer/vcosim/simenv/vpi directory. The set of those routines is defined in the `vpi_vcosim.c' file.

The names of the Vcosim VPI routines are $vt_vcosim_*, for example:

• $vt_vcosim_0
• $vt_vcosim_1d
• $vt_vcosim_2d
• $vt_vcosim_4d

The routines are named according to the number of arguments which are passed to them (0: zero arguments, 1d: 1 decimal argument, etc.).

The syntax of VPI routines is:

$vt_vcosim_<index>("Perl_subroutine_name", output, in_<0>, ..., in_<index-1>)

Here are some examples of calling those routines (the examples are taken from the Verilog mem_wrapper module):

• $vt_vcosim_1d("Vcosim::Mem_model::subSqr", val_return, val_arg_0);
  The val_return signal receives the squared value of the val_arg_0 signal's value.
• $vt_vcosim_2d("Vcosim::Mem_model::subMult", val_return, val_arg_0, val_arg_1);
  The val_return signal receives the product of val_arg_0 and val_arg_1 signal values.
• $vt_vcosim_0("Vcosim::Mem_model::subMemInit", val_return);
  The Perl routine initializes the memory model. No arguments are passed to the Perl routine. The value of val_return signal is irrelevant.
• $vt_vcosim_2d("Vcosim::Mem_model::subMemWr", val_return, mem_addr, data_c2m);
  Write to Perl memory model. The value of val_return signal is irrelevant.
• $vt_vcosim_1d("Vcosim::Mem_model::subMemRd", data_m2c_clean, mem_addr);
  Read from Perl memory model. The data_m2c_clean signal receives the memory data out value.

4.7 Vcosim data formats

Verilog syntax allows declarations of buses which size is more than 32 bits. The problem is that Perl stores numbers internally as either signed integers or double-precision floating-point values (see "Perl in a Nutshell" book, p.43). In order to avoid overflows, the sizes of buses passed as arguments to the Vcosim VPI routines must not exceed 32 bits limit.

Another problem is correct representation of hexadecimal values in Perl domain. For example, 0xffff_ffff Perl value, when passed through the VPI routine to a Verilog 32-bit bus, is changed to 0x7fff_ffff.
In order to preserve the original 0xffff_ffff value, you should direct Perl to store this value internally as a long integer, using the following Perl instruction:

sprintf("%ld", 0xffff_ffff)

$Id: vcosim_spec.texi,v 1.6 2004/12/03 19:46:57 danny_n Exp $