5. Other subprojects

These are the older projects.

Note: Vcdparser subproject is not functional any more !!!

5.1 Vcdparser
5.2 Vparser

5.1 Vcdparser

5.1.1 Vcdparser introduction
5.1.2 Vcdparser system requirements
5.1.3 Configuration file
5.1.4 Client-server running model
5.1.5 Vcdparser running flow
5.1.6 User commands manual

5.1.1 Vcdparser introduction

Vcdparser is a subproject of VTracer package. This subproject is based upon VCD (dump) format parser.

Sample design integrated into the Testbench is risc8 (free RISC core, currently not available (?)).

VCD is a standard signal trace format for HDL simulations. Often, there is a need to compare behavior of 2 different models which are supposed to work similarly. For example, when a Verilog core design is modified, there is a need to verify that output pins of both cores, the original and the modified, if supplied the same stimulus, behave exactly the same. But the usual problem is that the testbenches for each model are different, and the behavors are slightly different, for example, shifted by a constant value.

Vcdparser includes a set of configurable Perl scripts which performs comparison between pairs of signals from 2 different VCD files. The package includes a sample Tesbench demonstrating the integration of the tool.

The Vcdparser can be used for many different Testbench-related tasks. Here are some examples for what can be done with Vcdparser:

1. VComp flow performs comparison of results from 2 different simulations. Each simulation creates its VCD file, and the appropriate pairs of signals from the 2 VCD files are compared.

2. VStim flow creates a stimuli file from VCD generated by the original Testbench. This stimuli is used to feed the device into the new Testbench, thus applying to the device the same inputs as the native Testbench. The outputs of device under test from both simulations are compared by VComp flow. In addition, the VStim flow generates "chip_signals" module, which is a collection of pointers to signals appearing recorded into the VCD file.

5.1.2 Vcdparser system requirements

• Vcdparser subproject works with Icarus Verilog simulator.

• The subproject was tested on RedHat Linux 7.2

5.1.3 Configuration file

The configuration file (`archive/vcdparser/simenv/cfg/VTracer_flow.cfg') controls the behavior of the Vcdparser package. This file contains a set of proprietry instrunctions (ex., exit).
Various types of comments can be used in the file (--, #, //).

5.1.4 Client-server running model

When Vcdparser tool runs, there are 2 interconnected processes running simultaneously, the server and the client. Client/server communication is based upon TCP socket inter-process communication (by default, socket number 8081 is used). The server script is `archive/vcdparser/bin/user_frontend.tcl' script, the client is `archive/vcdparser/bin/run_proj.pl' script. The user runs the server script; the client is launched automatically by the server. The user communicates with the Vcdparser via server only. Vcdparser commands, explained below, can be executed either through shell-like interactive interface, or by editing the configuration file (`archive/vcdparser/simenv/cfg/Vtracer_flow.cfg') or by running it using run_cfg <cfg_filename> instruction.

exit instruction can be used anytime during the flow. This instruction terminates the flow.

The configuration can be freely modified, by remarking certain instructions / sections, thus creating an flow optimized for performing certain tasks.

5.1.5 Vcdparser running flow

• The running flow starts from this directory:

  cd archive/vcdparser

• Server invocation:

  ../bin/user_frontend.tcl

• Run Verilog simulation, create VCD file(s). When the prompt is displayed, print:

  run_cfg ../simenv/cfg/run_sim.cfg

• Display design information. When the prompt is displayed, print:

  run_cfg ../simenv/cfg/print_info.cfg

• VComp flow. When the prompt is diplayed, print:

  run_cfg ../simenv/cfg/VTracer_flow.cfg

  This flow compares signals from 2 different VCD files (`risc8_orig' and `risc8_modif' simulations).

• VStim flow. When the prompt is diplayed, print:

  run_cfg ../simenv/cfg/stim_gen.cfg

• `stim_dat.v' (simulation stimuli) and `chip_signals.v' (signals pointers file) are generated.

  cp stim_data.v archive/vcdparser/simenv/tb/stim_data_ref.v
cp chip_signals.v archive/vcdparser/simenv/tb/chip_signals.v

• Edit the `../simenv/cfg/run_sim.cfg' file and run `risc8_modif' configuration only:

  run_cfg ../simenv/cfg/run_sim.cfg

• Run signals comparison (VComp) flow:

  run_cfg ../simenv/cfg/VTracer_flow.cfg

5.1.6 User commands manual

Here is a manual of user commands, in alphabetical order. These commands can be used during the flow, through the server-client interface.

debug_mode <mode>

Set debug mode (0/1).

exit

Exit the Vcdparser flow.

fname_vcd <filename_vcd_0> <filename_vcd_1>

Read VCD files, 0 (reference, "golden" model) and 1 (target design).

get_sig_trace

Read signal's trace data into the database.

license

Display license information.

mode_shift <time_0> <time_1>

"trace shift" settings.

print_full_sig_names

Print full signal names.

print_hier

Print design hierarchy. VCD file used: no. 0.

print_sig_data

Print signals database.

print_sig_trace

Print signal trace data.

run_cfg <cfg_filename>

Run configuration file.

set_cur_hier <hierarchy_name>

Set hierarchy level to be found.

set_cur_sig_name <signal_name>

Set signal name to be found (from the previously defined hierarchy level !!!)

set_design_name <design_name>

Design name setting.

sig_cmp_pair <signal_0> <signal_1>

Compare pair of signals.

sig_ptr_gen <file_name> <module_name>

"signal pointers" module generation (chip_signals).

stim_gen <stim_file_name> <stim_module_name> <reference_module_name>

Stimuli generation.

time_cmp_start <time>

set comparison start time.

time_jitter <time>

Set time jitter variable.

timeout <time>

Set timeout parameter.

timescale_adjust <time_parameter>

Set "timescale adjust" parameter.

vlog_compile

Verilog compilation.

vlog_sim

Run Verilog simulation.

vcd_read

Read VCD file(s).

view_dump_virsim

display dump (VCD) file, with VCS VirSim viewer.

$Id: vcdparser_spec.texi,v 1.4 2004/12/12 12:05:46 dannyn Exp $

5.2 Vparser

5.2.1 Vparser introduction
5.2.2 Vparser system requirements
5.2.3 Vparser running flow

5.2.1 Vparser introduction

Vparser is based on a structural Verilog parser (netlist). The parser itself is written in Perl.

Sample design integrated into the Testbench is risc8 (free RISC core, currently not available (?)).

5.2.2 Vparser system requirements

Additional tools which should be installed:

• Verilog::Perl Perl module.

5.2.3 Vparser running flow

• The running flow starts from this directory:

  cd archive/vparser

• Build database file, for future queries invocation:

  ../bin/vlog_parse.pl -build

• Load the pre-built database file, and run the queries:

  ../bin/vlog_parse.pl -load

$Id: vparser_spec.texi,v 1.3 2004/12/03 16:11:02 danny_n Exp $